The present invention relates to a thin film transistor array substrate and a method of manufacturing the same. More particularly, the present invention relates to a method of manufacturing a thin film transistor array substrate having less point defect and line defect and capable of reducing a leakage current of a thin film transistor (TFT) by carrying out a photolithographic process four times, and enhances the display characteristic and productivity of a TFT-LCD.
An electro-optic element using a liquid crystal has been vigorously applied to a display. The electro-optic element using the liquid crystal generally has such a structure that the liquid crystal interposed between two substrates including electrodes in a vertical direction and a polarizing plate is provided in the vertical direction. In a transmission type, a back light is provided on a back face. The surfaces of the upper and lower electrode substrates are subjected to a so-called orientation processing, and a director to be an average direction of a liquid crystal molecule is controlled to be brought into a desirable initial state. The liquid crystal has a double refracting property, and a light incident through the polarizing plate from the back light is changed into an elliptically polarized light through the double refraction and is then incident on the polarizing plate on the opposite side. When a voltage is applied to the upper and lower electrodes in this state, the state of array of the director is changed so that a double refractive index of a liquid crystal layer is changed and the state of the elliptically polarized light incident on the polarizing plate on the opposite side. Accordingly, an intensity of the light transmitted through the electro-optic element and a spectrum thereof are varied. The electro-optic effect is varied depending on the type of a liquid crystal layer, an initial orientation state, the direction of an polarizing axis of the polarizing plate, a thickness of the liquid crystal layer or a color filter provided in the middle of a light transmission path or various interference films, which has been reported in detail by well-known papers or the like. In general, a structure referred to as TN or STN using a nematic liquid crystal layer is used.
Examples of an electro-optic element for a display using a liquid crystal include a simple matrix type and a TFT-LCD using a thin film transistor (TFT) as a switching element. The TFT-LCD having more characteristics than those of a CRT and a simple matrix type liquid crystal display in respect of portability and display quality has been widely put into practical use for a notebook type personal computer. The TFT-LCD generally has such a structure that a liquid crystal is interposed between a TFT array substrate having a TFT formed like an array and an opposed substrate having a color filter which is provided with a common electrode, a polarizing plate is provided above and under the structure, and furthermore, a back light is provided on the back. With such a structure, excellent color display can be obtained.
In order to apply a voltage to the liquid crystal in the TFT-LCD, the TFT is turned ON within a gate line selection time and electric charges are caused to flow from a source line to a pixel electrode and a pixel potential is set to be equal to the electric potential of the source line. Then, when a gate is brought into a non-selection state, the TFT is turned OFF so that the electric charges of a pixel are held. Actually, the amount of the electric charges of the pixels is decreased by the TFT and the leakage current in the liquid crystal. As a result, the electric potential of the pixel is reduced. In order to prevent the electric potential of the pixel from fluctuating, an auxiliary capacitor is usually provided to reduce the amount of a change in the electric potential of the pixel for a change in a unit charge amount is reduced. Moreover, a trial to decrease the number of FTF array manufacturing steps has been made to enhance the productivity of the TFT-LCD. A trial to eliminate a photolithographic step has been disclosed in Japanese Unexamined Patent Publication No. 202153/1994, Japanese Unexamined Patent Publication No. 328040/1996 and Japanese Unexamined Patent Publication No. 50308/1996.
FIG. 57 is a sectional view showing a pixel portion of a TFT array substrate manufactured at a five-time photolithographic step disclosed in a seventh embodiment of the Japanese Unexamined Patent Publication No. 50308/1996. In the conventional example, first of all, a first conductive metallic thin film such as Cr, Ta, Mo or Al is formed in a thickness of approximately 100 nm on a transparent substrate. Next, the first conductive metallic thin film is subjected to patterning at a first photolithographic step, thereby forming a gate electrode 51. At this time, if the first conductive metallic thin film is Cr, a wet etching treatment is carried out by using a (NH4)2[Ce(NO3)6]+HNO3+H2O solution, for example. Then, a SiNx film, an a-Si film and an n+a-Si film are provided in thicknesses of approximately 300 nm, 100 nm and 20 nm as a first insulating film 52, a semiconductor active film 53 and an ohmic contact film 54, respectively. At a second photolithographic step, next, the semiconductor active film 53 and the ohmic contact film 54 are subjected to patterning like an island in a state in which a semiconductor portion is isolated from other portions above a gate electrode. At this time, the semiconductor active film and the ohmic contact film are subjected to dry etching with SF6+HCl+He, for example.
Next, a second metallic thin film such as Ti is formed in a thickness of approximately 300 nm. Then, the second metallic thin film and the ohmic contact film are subjected to patterning at a third photolithographic step so that a source line 55, a source electrode 56, a drain electrode 57 and a semiconductor active layer 58 of a thin film transistor are formed. Subsequently, an interlayer insulating film (passivation film) 59 is formed in a thickness of approximately 400 nm by a method such as plasma CVD. Next, the passivation film is subjected to the patterning at a fourth photolithographic step so that a contact hole 60 communicating with the drain electrode 57, a contact hole communicating with a gate line and a contact hole communicating with a source line are formed. At this time, the passivation film is subjected to the etching through dry etching using SF6+O2 or the like, for example. Then, a transparent conductive film comprising ITO is formed in a thickness of approximately 150 nm. Thereafter, the transparent conductive film is subjected to the patterning at a fifth photolithographic step to form a transparent pixel electrode 61, a terminal portion for source line connection and a terminal portion for gate line connection. At this time, the ITO film is subjected to wet etching by using an HCl+HNO3+H2O solution, for example.
In the conventional art, thus, the method of manufacturing a TFT array at five photolithographic steps has been disclosed. The following effects have been described. More specifically, the five photolithographic steps are enough, resulting in an enhancement in yield and a reduction in cost. In addition, since the passivation film is not provided on the transparent pixel electrode, a voltage can be applied efficiently to the liquid crystal. Furthermore, since the transparent pixel electrode, the source line and the gate line are isolated from each other through an insulating film, there is no possibility that the source lines or the gate lines might be short-circuited due to the defective formation of the transparent pixel electrode. As the effects of the conventional art, moreover, the following has been described. More specifically, in the case in which a multilayered film of a metallic thin film and a barrier film made of a material oxidized or a material solidified as a conductive oxide to the transparent conductive film is sued for a first conductive metallic thin film, the barrier film further produces antioxidant effects to maintain contact property of these films with the transparent conductive film. Therefore, a signal delay is caused signal delay with difficulty. Furthermore, Al or Ta having high conductive property is used as a metallic thin film to reduce a thickness of the metallic thin film. Consequently, a step coverage of the whole TFT element can be enhanced and yield can be improved. In the TFT array structure, the gate line, the source line and the pixel electrode are isolated from each other through the insulating film. Therefore, there is also an advantage that a short-circuit is generated with difficulty and the yield can easily be enhanced.
FIGS. 59(a) to 59(c), 60(a) to 60(c) and 61(a) to 61(d) show an example of the TFT array structure to be used for a conventional active matrix type liquid crystal display (AMLCD). FIGS. 59(a) to 59(c) and 60(a) to 60(c) are an example of sectional views, FIG. 61(a) to 61(d) is a plan view, and FIGS. 59(a) to 59(c) and 60(a) to 60(c) show sectional structures of X—X in FIG. 61(a) to 61(d) and a gate-source terminal portion.
In FIGS. 59(a) to 59(c), 60(a) to 60(c) and 61(a) to 61(d), the reference numeral 311 denotes an insulating substrate, the reference numeral 313 denotes a gate electrode and a gate line, the reference numeral 314 denotes a pixel electrode formed of a transparent conductive film, the reference numeral 316 denotes a gate insulating film, the reference numeral 317 denotes a semiconductor layer (active layer), the reference numeral 318 denotes a semiconductor layer (ohmic contact layer) containing an impurity such as P or B, the reference numeral 322 denotes an insulating film such as SiN4, the reference numeral 330 denotes a contact hole, the reference numeral 302 denotes a source line, the reference numeral 303 denotes a source electrode, and the reference numeral 304 denotes a drain electrode.
Description will be given to a method of manufacturing a TFT array substrate to be used for a conventional active matrix liquid crystal display (AMLCD). A layer of a substance comprising a metal such as Cr, Al or Mo, an alloy having them as a main component, a metal having them multilayered or the like is formed on the insulating substrate 311 by sputtering or the like. Next, a gate electrode, a gate line pattern 313 and the like are formed by using a photoresist or the like through photolithography and succeeding etching or the like (FIGS. 59(a) and 61(a)).
Next, an insulating film 316 comprising Si3N4, SiO2 or the like to be a gate insulating film formed by various CVD methods such as plasma CVD, sputtering, evaporation, coating or the like, a semiconductor layer 317 comprising an a-Si:H film (amorphous silicon hydride film), and an ohmic contact layer 318 comprising an n+a-Si:H film or a microcrystal n+Si layer to be a semiconductor layer formed by the plasma CVD or sputtering and doped with an impurity such as phosphorus, antimony boron in order to take a contact with a metal are continuously formed. Then, a semiconductor layer (active layer) 317 in as a TFT portion, a gate line-source line cross section and the like and a semiconductor layer (ohmic contact layer) 318 containing an impurity such as P or B are formed by photolithography and succeeding etching or the like using a photoresist or the like (FIGS. 59(b) and 61(b)).
Then, a transparent conductive layer formed of a transparent conductive material such as ITO (Indium Tin Oxide) is provided by sputtering, evaporation, a sol-gel method and the like. Thereafter, a pixel electrode 314, a terminal electrode and the like are formed by photolithography and succeeding etching or the like by using the photoresist or the like (FIGS. 59(c) and 61(c)).
Subsequently, a pattern is formed such that a contact hole can be provided in a gate terminal portion or the like by the photolithography using the photoresist or the like. Then, the gate insulating film 316 is removed by dry etching or the like using a CF4 based gas or the like. Thereafter, the photoresist is removed to form a contact hole 330 (see FIG. 60(a)).
Next, a layer of a substance comprising a metal such as Cr, Al or Mo, an alloy comprising them as a main component or a metal having them multilayered is formed by the sputtering or the like. Then, a source line 302, a source electrode 303 and a drain electrode 304 are formed by using the photoresist or the like through the photolithography and succeeding etching or the like (FIGS. 60(b) and 61(d)).
Thereafter, an insulating film 322 such as Si3N4, SiO2 or their multilayered layer, that is, Si3N4 to act as a gate insulating film is formed by various CVD methods such as plasma CVD, sputtering, evaporation, coating and the like. Next, a photoresist or the like is used to remove an insulating film in a terminal portion or the like through the photolithography and succeeding dry etching using a CF4 based gas or the like such that a signal can be input from an external TCP or the like to each wiring. Consequently, a TFT array is formed (FIG. 60(c)).
Subsequently, an orientation film is formed on the TFT array and counter electrodes are opposed and a liquid crystal is interposed therebetween. Thus, an active matrix type liquid crystal display is formed.
In the seventh embodiment of the Japanese Unexamined Patent Publication No. 50308/1996, there has been disclosed a technique in which the semiconductor layer 53 is isolated like an island. In the case in which a source line is formed of a single metal layer and is patterned by wet etching, etching liquid enters a metal and semiconductor interface from a step portion of the semiconductor layer to cause a disconnection if a source metal has poor adhesion in the step portion. As disclosed in Japanese Unexamined Patent Publication No. 268353/1998, it is preferable that a semiconductor pattern should be extended under the source line. FIG. 58 is a plan view showing a thin film transistor in which the semiconductor layer 53 is isolated. In general, a leakage current easily flows to a semiconductor end face. With such a structure, therefore, an end face leak path 62 provided from a source electrode 56 to a drain electrode 57 is present to increase a leakage current of the thin film transistor. Consequently, the display quality of a display is greatly affected, for example, a contrast is reduced, a luminescent spot is increased during use at a high temperature (in the case of normally white).
On the other hand, there has been disclosed a technique in which the photolithographic process is carried out five times in the state in which the gate line, the source line and the pixel electrode are isolated. However, a technique in which the photolithographic process is reduced has not been disclosed. It is an object of the present invention to carry out the photolithographic step four times while maintaining the above-mentioned structure, to have no semiconductor layer step under a source electrode or a source line and to efficiently prevent display defects from being caused by the end face leakage of the semiconductor layer, thereby maintaining display quality and yield, and furthermore, enhancing productivity.
Moreover, in the case in which the TFT array is to be formed by using a conventional manufacturing method, the photolithographic step should be carried out at least five times. Therefore, a manufacturing process is prolonged. In particular, there is a problem in that an exposing step having a high operation cost for production equipment is often used. For this reason, the cost of the TFT array to be fabricated is necessarily increased.
The present invention has been made to solve the above-mentioned problems of the conventional art, and has an object to decrease the number of photolithographic steps required for manufacturing the TFT array, and furthermore, to reduce the number of masks, thereby improving productivity and reducing a cost.
In the case in which the TFT array is to be fabricated by using a conventional manufacturing method, the photolithographic step should be carried out at least five times. Therefore, the manufacturing process is prolonged. In particular, there is a problem in that an exposing step having a high operation cost for production equipment is often used. For this reason, the cost of the TFT array to be fabricated is necessarily increased.
It is an object of the present invention to reduce the number of photolithographic steps (the number of masks) required for manufacturing the TFT array in order to enhance the productivity of an active matrix type liquid crystal display or to reduce a cost thereof.